1. Field of the Invention
The present invention generally relates to automating testability operation in connection with electronic design automation (EDA) software, and more particularly, to a graphical user interface (GUI) for testability operation.
2. Description of the Related Art
With astonishing regularity over the past several decades, transistors have become smaller and the devices that employ them have become more complex. Today it is not uncommon for an integrated circuit (IC) to contain millions of transistors. The job of designing these ICs has also grown correspondingly more difficult. What was once accomplished by a single individual or a small group of individuals is typically performed by a large team or multiple teams of design engineers.
Although very large scale integration (VLSI) circuits have become more difficult to design, a number of tools have been developed to make the job easier. One class of tools that is makes the job more manageable is called electronic design automation (EDA). Using an EDA tool, a design engineer can break a large circuit into smaller functional units and specify constraints and requirements such as desired inputs and outputs of the functional units. The EDA tool then suggests solutions, often drawing on a vast digital library of possible circuits. In this manner, large circuits are decomposed into more manageable units that can be designed individually, perhaps by groups of design engineers working more or less independently. The result is that the overall design process is significantly faster than it would be otherwise.
For example, Unified Design Automation, Inc. of Austin, Tex. publishes Silicon Arena, a software package that provides, among other things, a graphical synthesis environment in which a design engineer can constrain and synthesize a design using a set of templates for creating logic synthesis command scripts. Information relevant to a specific design may be stored in template files and compiled into a design run as needed. Silicon Arena provides a mechanism for maintaining and sharing synthesis scripts and parameters. Silicon Arena enables a user to create a gate-level netlist (a shorthand description of a schematic indicating connections among logic elements) including Design For Test (DFT) scan chains. In particular, the Silicon Arena synthesis page allows a user to configure synthesis constraints, compile high-level Register Transfer Level (RTL) code which takes into account the constraints, generate data for other teams of design engineers who place and route the design in light of the constraints, and generate schematics used for final circuit layout configuration. Silicon Arena thus gives a user the ability to easily constrain and synthesize a design using a known set of synthesis templates.
As circuits have become increasingly complex, DFT tools have become increasingly important by insuring the ability to test a circuit. Automated test tools such as FastScan and FlexTest both published by Mentor Graphics of Wilsonville, Oreg. have been developed to provide this functionality. During the design process, selected sequential elements such as flip-flops and latches are replaced with their scan equivalent elements. In addition, sets and resets are modified so that they are not asserted during testing, and three-state buses are modified to reduce bus conflicts. Also, an Automatic Test Pattern Generator (ATPG) may generate a set of xe2x80x9cscan vectorsxe2x80x9d to provide a high fault coverage of a circuit. More sophisticated testing procedures that employ scan flip-flops built into the circuit can perform testing at a functional unit level.
As the number of design tools has increased, a design engineer has typically been required to master a separate interface for each tool. This often includes learning interface commands and features for each different tool.
Briefly, a graphical user interface (GUI) provides a design engineer the capability of automatically inserting scan logic and test logic within a circuit design to be compiled by an electronic design automation (EDA) tool. Through the graphical user interface, a design engineer can invoke a scan insertion tool to check the design for testability and also can invoke a test generation tool to check for fault coverage. The graphical user interface can include a scan insertion option to initiate a scan insertion command script to invoke the scan insertion tool and a test generation option to initiate a test generation tool command script to invoke the test generation tool.
In view of the increased size and complexity of current electronic circuitry, it has become increasingly important to identify faults and test coverage problems in a circuit design as early as possible in the design process. The graphical user interface enables a design engineer to quickly insert scan into a design and identify testability and test coverage problems early in the design phase without the need for detailed knowledge of the scan insertion and test generation tools.
After a design engineer has completed a register transfer level (RTL) design of a design block, the design engineer may enable the scan insertion option during a compile. Subsequently, the design engineer may check for fault coverage by enabling the test generation option.
Prior to development of the following subject matter, there was no GUI for scan insertion. In addition, GUIs for ATPG were non-intuitive and did not interface with the synthesis flow. As a result, design engineers had to write scripts and learn extra commands. The GUI according to the present invention supports different DFT and Synthesis tools from multiple vendors and thus enables a design engineer to use different scan insertion, EDA and ATPG tools from multiple vendors by means of a standard interface, thus creating reproducible results and higher productivity.